According to John Markoff of The New York Times, today Intel will be demonstrating an experimental computer chip with 80 separate cores. This is going on at the Solid States Circuits Conferences in San Francisco today, and it’s stirring quite the buzz.  Before you get all excited, this is just a prototype, and currently it’s not compatible with the most recent Intel processors.  It can’t interact to external memory yet, but the plans are in the works to develop a commercial version.

The commercial version as expected, would be used in your desktops, laptops, servers, etc. Unfortunately, it will be at least five years before consumers will be able to get their hands on one. With 80 separate cores, what would you do with all that processing power? The possibilities would be endless, developers would have a lot of room to groove, and computer games would become more and more realistic.

It’s amazing to think that the Dual Core processors are just starting to get around, and yet the Teraflop chip is already in the works. And according to Gizmodo, at 1 trillion calculations per second, the 80-core chip would be able to do the same amount of calculations as 2,000 square feet of machinery could do 10 years ago.

One question that needs to be asked is whether or not increasing the cores will increase the performance. Markoff says, “In a white paper published last December, the scientists said that without a software breakthrough to take advantage of hundreds of cores, the industry, which is now pursuing a more incremental approach of increasing the number of cores on a computer chip, is likely to hit a wall of diminishing returns — where adding more cores does not offer a significant increase in performance.”

This chip would be air-cooled, and definitely raises the bar for the industry. While an 80 core processor may seem like a lot, with the way ’some’ of the current operating systems are going, it wouldn’t be. The processors tend to evolve right along side the operating systems, and as more processing power becomes available, bloated operating systems take full advantage of the resources.

Source: The New York Times

  1. And I still have a single core… :cry:

  2. Multi-core madness begins… With modern microprocessor architecture, it is SIMPLE to create such multi-core CPUs. I’m sure, this year we will see 800-core CPUs. Who’s next? AMD? AMD will create something MUCH BIGGER very soon, maybe we have to wait no longer than 1 month. Remember my words.

  3. BTW, Speed evolution is almost over. No more GHz’s growing. Now it is time for multi-core CPUs.

  4. SLA wrote:
    AMD will create something MUCH BIGGER very soon, maybe we have to wait no longer than 1 month.

    My guess is that they already have something similar, but instead of unveiling and showing off the technology to their rivals they would rather keep it hush hush and surprise Intel with their work. I could see something big happening like Intel releasing 8 cores and then just days later AMD releases 16 cores to the consumers. Boy would Intel be embarrassed.

  5. For the REAL future of processors, check out [cs.utexas.edu]~trips/, the highly acclaimed and awarded architecture. The key to exploiting all the cores? Dataflow.
    Let me explain: The real problem inhibiting exploitation of parallel computations is dependencies. Although programs are written to be executed in sequential order, most have large portions of inherently parallel instructions – it is not necessary to execute these instructions in any order to maintain correctness. However, it is very difficult to detect these dependencies (multi-core puts this burden on the programmer) and thus, exploit the parallelism. To make matters worse, even when dependencies are detected, the next defendant instruction must wait for the earlier one to write back to memory so it can read its result. While a few more cpu cycles are wasted writing and reading the results, we leave some computational units with nothing to do. Poor little guys.
    The idea behind dataflow (and by extension, TRIPS) is to try to keep these guys busy as much as possible. So instead of writing back to memory for every computation, we just forward the answer to whatever instructions in flight need it next. The result? A highly scalable architecture (it is easy to add new computational units) that has many executions in flight.
    There are many other details important to the TRIPS’ performance, but dataflow is the basic idea for the entire design.
    The best thing about this design, is that it can (and is) easily combined with standard multi-processor techniques to allow for even more computational power.

    Also, Intel’s display isn’t impressive when you consider IBM has already prototyped a processor with many more cores.